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Deleteddoc/COPYRIGHT +0−20
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1 {+-----------------------------------------------------------------------------
2 |
3 | The autho makes no representations about the suitability of this software
4 | for any purpose. It is provided "as is" without express or implied
5 | warranty.
6 |
7 | THE COPYRIGHT HOLDER DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
8 | INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
9 | EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY SPECIAL, INDIRECT OR
10 | CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
11 | DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
12 | TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
13 | PERFORMANCE OF THIS SOFTWARE.
14 |
15 +----------------------------------------------------------------------------+
16 |
17 | The Mapviewer has been taken from VGBC and it�s Copyrighted by
18 | Rusty Wagner !
19 | The AGOpenDialog-Component is Copyrighted by Deepak Shenoy
20 +----------------------------------------------------------------------------+}
Deleteddoc/ChangeLog +0−21
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1 Additions to the emulator, from the first version that was released.
2 Names between brackets are games that first indicated the presence
3 of the corresponding bug in the emulator, or the person
4 that spotted the bug.
5
6 o - new function
7 x - fixed bug
8
9
10 Version 0.1
11 -----------
12
13 o First release
14
15 Version 0.2
16 -----------
17
18 o Sound emulation
19 o Realspeed fix
20 o Dib-Output
21 o Map-Viewer
Deleteddoc/GBSPEC.TXT +0−1377
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1 ============================================================================
2 Everything You Always Wanted To Know About GAMEBOY *
3 ==============================================================================
4
5 * but were afraid to ask
6
7
8 Pan Document Updated
9
10 Last update 25-Sept-97 by kOOPa
11
12 Forward: The following was typed up for informational purposes regarding
13 the inner workings on the hand-held game machine known as
14 GameBoy, manufactured and designed by Nintendo Co., LTD.
15 This info is presented to inform a user on how their Game Boy
16 works and what makes it "tick". GameBoy is copyrighted by
17 Nintendo Co., LTD. Any reference to copyrighted material is
18 not presented for monetary gain, but for educational purposes
19 and higher learning.
20
21
22 Game Boy Specs
23 --------------
24
25 CPU: 8-bit (Similiar to the Z80 processor.)
26 Main RAM: 8K Byte
27 Video RAM: 8K Byte
28 Screen Size 2.6"
29 Resolution: 160x144
30 Max # of sprites: 40
31 Max # sprites/line: 10
32 Max sprite size: 8x16
33 Min sprite size: 8x8
34 Clock Speed: 4.194304 MHz
35 Sound: 4 channels with stereo sound
36 Power: DC6V 0.7W
37
38
39 Processor
40 ---------
41
42 The GameBoy uses a computer chip similiar to an Intel 8080.
43 It contains all of the instructions of an 8080 except there
44 are no exchange instructions. In many ways the processor is
45 more similiar to the Zilog Z80 processor. Compared to the
46 Z80, some instructions have been added and some have been
47 taken away.
48
49 The following are new instructions:
50
51 LDI (HL),#$xx
52 LDD (HL),#$xx
53 SWAP A through L
54 LD A,($FFxx)
55
56 The following instructions have been removed:
57
58 Any command that uses the IX or IY registers.
59 All input or output instructions.
60 All exchange instructions.
61 All 'jp' or 'call' instructions based on M or P flags.
62
63 The following instructions have changed:
64
65 'ld a,[x]' and 'ld [x],a' have different opcodes.
66 'reti' has a different opcode.
67
68
69 General Memory Map* Hardware Write Registers
70 ------------------ ------------------------
71
72 Interrupt Enable Register
73 --------------------------- FFFF
74 Internal RAM
75 --------------------------- FF80
76 Empty but unusable for I/O
77 --------------------------- FF4C
78 I/O ports
79 --------------------------- FF00
80 Empty but unusable for I/O
81 --------------------------- FEA0
82 Sprite Attrib Table (OAM)
83 --------------------------- FE00
84 Echo of 8kB Internal RAM
85 --------------------------- E000
86 8kB Internal RAM
87 --------------------------- C000 -------------------------
88 8kB switchable RAM bank / MBC1 ROM/RAM Select
89 --------------------------- A000 / ------------------------
90 8kB Video RAM / / RAM Bank Select
91 --------------------------- 8000 --/ / -----------------------
92 16kB switchable ROM bank 6000 ----/ / ROM Bank Select
93 --------------------------- 4000 ------/ ----------------------
94 16kB ROM bank #0 2000 --------/ RAM Bank enable
95 --------------------------- 0000 -------------------------------
96
97 * NOTE: b = bit, B = byte
98
99
100 Echo of 8kB Internal RAM
101 ------------------------
102
103 The addresses E000-FE00 appear to access the internal RAM
104 the same as C000-DE00. (i.e. If you write a byte to address
105 E000 it will appear at C000 and E000. Similarly, writing a
106 byte to C000 will appear at C000 and E000.)
107
108
109 User I/O
110 --------
111
112 There are no empty spaces in the memory map for
113 implementing input ports except the switchable RAM bank
114 area (not an option on the Super Smart Card since it's
115 RAM bank is always enabled).
116
117 An output only port may be implemented anywhere between
118 A000-FDFF. If implemented in a RAM area care should be
119 taken to use an area of RAM not used for anything else.
120 (FE00 and above can't be used because the CPU doesn't
121 generate an external /WR for these locations.)
122
123 If you have a cart with an MBC1, a ROM 4Mbit or smaller,
124 and a RAM 8Kbyte or smaller (or no RAM) then you can use
125 pins 6 & 7 of the MBC1 for 2 digital output pins for
126 whatever purpose you wish. To use them you must first
127 put the MBC1 into 4MbitROM/32KbyteRAM mode by writing
128 01 to 6000. The two least significant bits you write
129 to 4000 will then be output to these pins.
130
131
132 Cart Memory Info
133 ----------------
134
135 0040 Vertical Blank Interrupt Start Address
136
137 0048 LCDC Status Interrupt Start Address
138
139 0050 Timer Overflow Interrupt Start Address
140
141 0058 Serial Transfer Completion Interrupt Start Address
142
143 0060 High-to-Low of P10-P13 Interrupt Start Address
144
145 An internal information area is located at 0100-014F in
146 each cartridge. It contains the following values:
147
148 0100-0103 This is the begin code execution point in a
149 cart. Usually there is a NOP and a JP
150 instruction here but not always.
151
152 0104-0133 Scrolling Nintendo graphic:
153 CE ED 66 66 CC 0D 00 0B 03 73 00 83 00 0C 00 0D
154 00 08 11 1F 88 89 00 0E DC CC 6E E6 DD DD D9 99
155 BB BB 67 63 6E 0E EC CC DD DC 99 9F BB B9 33 3E
156 ( PROGRAM WON'T RUN IF CHANGED!!!)
157
158 0134-0143 Title of the game in UPPER CASE ASCII. If it
159 is less than 16 characters then the remaining
160 bytes are filled with 00's.
161
162 0144 Ascii hex digit, high nibble of licensee code.
163 0145 Ascii hex digit, low nibble of licensee code.
164
165 Note: 0144-0145 are zero for non-super gameboy games.
166
167 0146 SGB features (00 = GameBoy, 03 = Super GameBoy functions)
168
169
170 0147 Cartridge type:
171 0 - ROM ONLY 5 - ROM+MBC2
172 1 - ROM+MBC1 6 - ROM+MBC2+BATTERY
173 2 - ROM+MBC1+RAM 8 - ROM+RAM
174 3 - ROM+MBC1+RAM+BATTERY 9 - ROM+RAM+BATTERY
175 FF - ROM+HuC1+RAM+BATTERY
176
177 0148 ROM size:
178 0 - 256Kbit = 32KByte = 2 banks
179 1 - 512Kbit = 64KByte = 4 banks
180 2 - 1Mbit = 128KByte = 8 banks
181 3 - 2Mbit = 256KByte = 16 banks
182 4 - 4Mbit = 512KByte = 32 banks
183 5 - 8Mbit = 1MByte = 64 banks
184 6 - 16Mbit = 2MByte = 128 banks
185 52 - 9Mbit = 1.1MByte = 72 banks
186 53 - 10Mbit = 1.2MByte = 80 banks
187 54 - 12Mbit = 1.5MByte = 96 banks
188
189 0149 RAM size:
190 0 - None
191 1 - 16kBit = 2kB = 1 bank
192 2 - 64kBit = 8kB = 1 bank
193 3 - 256kBit = 32kB = 4 banks
194
195 014A Destination code:
196 0 - Japanese
197 1 - Non-Japanese
198
199 014B Licensee code:
200 33 - Super GameBoy game.
201 Check 0144/0145 for Licensee code.
202 79 - Accolade
203 A4 - Konami
204
205 014C Mask ROM Version number
206
207 014D Complement check
208 (PROGRAM WON'T RUN IF NOT CORRECT!!!)
209
210 014E-014F Checksum (higher byte first) produced by
211 adding all bytes of a cartridge except for two
212 checksum bytes and taking two lower bytes of
213 the result. (GameBoy ignores this value.)
214
215
216 Cartridge Types
217 ---------------
218
219 The following define the byte at cart location 0147:
220
221 ROM ONLY
222 This is a 32kB (256kb) ROM and occupies 0000-7FFF.
223
224 MBC1 (Memory Bank Controller 1)
225 MBC1 has two different maximum memory modes:
226 16Mbit ROM/8KByte RAM or 4Mbit ROM/32KByte RAM.
227
228 The MBC1 defaults to 16Mbit ROM/8KByte RAM mode
229 on power up. Writing a value (XXXXXXXS - X = Don't
230 care, S = Memory model select) into 6000-7FFF area
231 will select the memory model to use. S = 0 selects
232 16/8 mode. S = 1 selects 4/32 mode.
233
234 Writing a value (XXXBBBBB - X = Don't cares, B =
235 bank select bits) into 2000-3FFF area will select an
236 appropriate ROM bank at 4000-7FFF. Values of 0 and 1
237 do the same thing and point to ROM bank 1. Rom bank 0
238 is not accessible from 4000-7FFF and can only be read
239 from 0000-3FFF.
240
241 If memory model is set to 4/32:
242 Writing a value (XXXXXXBB - X = Don't care, B =
243 bank select bits) into 4000-5FFF area will select an
244 appropriate RAM bank at A000-C000. Before you can
245 read or write to a RAM bank you have to enable it by
246 writing a XXXX1010 into 0000-1FFF area*. To disable
247 RAM bank operations write any value but XXXX1010
248 into 0000-1FFF area. Disabling a RAM bank probably
249 protects that bank from false writes during power
250 down of the GameBoy. (NOTE: Nintendo suggests values
251 0A to enable and 00 to disable RAM bank!!)
252
253 If memory model is set to 16/8 mode:
254 Writing a value (XXXXXXBB - X = Don't care, B =
255 bank select bits) into 4000-5FFF area will set the
256 two most significant ROM address lines.
257
258 * NOTE: The Super Smart Card doesn't require this
259 operation because it's RAM bank is ALWAYS enabled.
260 Include this operation anyway to allow your code
261 to work with both.
262
263 MBC2 (Memory Bank Controller 2):
264 This memory controller works much like the MBC1
265 controller with the following exceptions:
266
267 MBC2 will work with ROM sizes up to 2Mbit.
268
269 Writing a value (XXXXBBBB - X = Don't cares, B =
270 bank select bits) into 2000-3FFF area will select an
271 appropriate ROM bank at 4000-7FFF.
272
273 RAM switching is not provided. Unlike the MBC1 which
274 uses external RAM, MBC2 has 512 x 4 bits of RAM which
275 is in the controller itself. It still requires an
276 external battery to save data during power-off though.
277
278 The least significant bit of the upper address byte
279 must be zero to enable/disable cart RAM. For example
280 the following addresses can be used to enable/disable
281 cart RAM:
282 0000-00FF, 0200-02FF, 0400-04FF, ..., 1E00-1EFF.
283 The suggested address range to use for MBC2 ram
284 enable/disable is 0000-00FF.
285
286 The least significant bit of the upper address byte
287 must be one to select a ROM bank. For example the
288 following addresses can be used to select a ROM bank:
289 2100-21FF, 2300-23FF, 2500-25FF, ..., 3F00-3FFF.
290 The suggested address range to use for MBC2 rom
291 bank selection is 2100-21FF.
292
293
294 Power Up Sequence
295 -----------------
296
297 When the GameBoy is powered up, a 256 byte program
298 starting at memory location 0 is executed. This program
299 is located in a ROM inside the GameBoy. The first thing
300 the program does is read the cartridge locations from
301 $104 to $133 and place this graphic of a Nintendo logo
302 on the screen at the top. This image is then scrolled
303 until it is in the middle of the screen. Two musical
304 notes are then played on the internal speaker. Again,
305 the cartridge locations $104 to $133 are read but this
306 time they are compared with a table in the internal rom.
307 If any byte fails to compare, then the GameBoy stops
308 comparing bytes and simply halts all operations. If all
309 locations compare the same, then the GameBoy starts
310 adding all of the bytes in the cartridge from $134 to
311 $14d. A value of 25 decimal is added to this total. If
312 the least significant byte of the result is a not a
313 zero, then the GameBoy will stop doing anything. If it
314 is a zero, then the internal ROM is disabled and
315 cartridge program execution begins at location $100
316 with AF=$01B0, BC=$0013, DE=$00D8, HL=$014D and
317 Stack Pointer=$FFFE.
318
319
320 Low-Power Mode
321 --------------
322
323 It is recommended that the HALT instruction be used
324 whenever possible to reduce power consumption & extend
325 the life of the batteries. This command stops the
326 system clock reducing the power consumption of both
327 the CPU and ROM.
328 The CPU will remain suspended until an interrupt
329 occurs at which point the interrupt is serviced and
330 then the instruction immediately following the HALT
331 is executed.
332
333
334 Video
335 -----
336
337 The main GameBoy screen buffer (aka background) consists
338 of 256x256 pixels or 32x32 tiles (8x8 pixels each). Only
339 160x144 pixels can be displayed on the screen. Registers
340 SCROLLX and SCROLLY hold the coordinates of background to
341 be displayed in the left upper corner of the screen.
342 Background wraps around the screen (i.e. when part of it
343 goes off the screen, it appears on the opposite side.)
344
345 An area of VRAM known as Background Tile Map contains
346 the numbers of tiles to be displayed. It is organized as
347 32 rows of 32 bytes each. Each byte contains a number of
348 a tile to be displayed. Tile patterns are taken from the
349 Tile Data Table located either at 8000-8FFF or
350 8800-97FF. In the first case, patterns are numbered with
351 unsigned numbers from 0 to 255 (i.e. pattern #0 lies at
352 address 8000). In the second case, patterns have signed
353 numbers from -128 to 127 (i.e. pattern #0 lies at address
354 9000). The Tile Data Table address for the background
355 can be selected via LCDC register.
356
357 Besides background, there is also a "window" overlaying
358 the background. The window is not scrollable i.e. it is
359 always displayed starting from its left upper corner. The
360 location of a window on the screen can be adjusted via
361 WNDPOSX and WNDPOSY registers. Screen coordinates of the
362 top left corner of a window are WNDPOSX-7,WNDPOSY. The
363 tile numbers for the window are stored in the Tile Data
364 Table. Both the Background and the window share the same
365 Tile Data Table.
366
367 Both background and window can be disabled or enabled
368 separately via bits in the LCDCONT register.
369
370 The tile images are stored in the Tile Pattern Tables.
371 Each 8x8 image occupies 16 bytes, where each 2 bytes
372 represent a line:
373
374 Tile: Image:
375
376 .33333.. .33333.. -> 01111100 -> 7Ch
377 22...22. 01111100 -> 7Ch
378 11...11. 22...22. -> 00000000 -> 00h
379 2222222. <-- digits 11000110 -> C6h
380 33...33. represent 11...11. -> 11000110 -> C6h
381 22...22. color 00000000 -> 00h
382 11...11. numbers 2222222. -> 00000000 -> 00h
383 ........ 11111110 -> FEh
384 33...33. -> 11000110 -> C6h
385 11000110 -> C6h
386 22...22. -> 00000000 -> 00h
387 11000110 -> C6h
388 11...11. -> 11000110 -> C6h
389 00000000 -> 00h
390 ........ -> 00000000 -> 00h
391 00000000 -> 00h
392
393 As it was said before, there are two Tile Pattern Tables
394 at 8000-8FFF and at 8800-97FF. The first one can be used
395 for sprites and the background. Its tiles are numbered
396 from 0 to 255. The second table can be used for the
397 background and the window display and its tiles are
398 numbered from -128 to 127.
399
400
401 Sprites
402 ------
403
404 GameBoy video controller can display up to 40 sprites
405 either in 8x8 or in 8x16 pixels. Because of a limitation
406 of hardware, only ten sprites can be displayed per scan
407 line. Sprite patterns have the same format as tiles, but
408 they are taken from the Sprite Pattern Table located at
409 8000-8FFF and therefore have unsigned numbers. Sprite
410 attributes reside in the Sprite Attribute Table (aka OAM)
411 at FE00-FE9F. OAM is divided into 40 4-byte blocks each
412 of which corresponds to a sprite.
413
414 When sprites with different x coordinate values overlap,
415 the one with the smaller x coordinate (closer to the left)
416 will have priority and appear above any others.
417
418 When sprites with the same x coordinate values overlap,
419 they have priority according to table ordering. (i.e.
420 FE00 - highest, FE04 - next highest, etc.)
421
422 Blocks have the following
423 format:
424
425 Byte0 Y position on the screen
426 Byte1 X position on the screen
427 Byte2 Pattern number 0-255 [notice that unlike tile
428 numbers, sprite pattern numbers are unsigned]
429 Byte3 Flags:
430
431 Bit7 Priority
432 If this bit is set to 0, sprite is displayed
433 on top of background & window. If this bit
434 is set to 1, then sprite will be hidden behind
435 colors 1, 2, and 3 of the background & window.
436 (Sprite only prevails over color 0 of BG & win.)
437 Bit6 Y flip
438 Sprite pattern is flipped vertically if
439 this bit is set to 1.
440 Bit5 X flip
441 Sprite pattern is flipped horizontally if
442 this bit is set to 1.
443 Bit4 Palette number
444 Sprite colors are taken from OBJ1PAL if
445 this bit is set to 1 and from OBJ0PAL
446 otherwise.
447
448
449 Sprite RAM Bug
450 --------------
451
452 There is a flaw in the GameBoy hardware that causes
453 trash to be written to OAM-RAM if the following commands
454 are used while their 16-bit content is in the range
455 of $FE00 to $FE9F:
456
457 inc xx (xx = bc,de, or hl)
458 dec xx
459
460 ldi a,(hl)
461 ldd a,(hl)
462
463 ldi (hl),a
464 ldd (hl),a
465
466
467 Sound
468 -----
469
470 There are two sound channels connected to the output
471 terminals SO1 and SO2. There is also a input terminal Vin
472 connected to the cartridge. It can be routed to either of
473 both output terminals. GameBoy circuitry allows producing
474 sound in four different ways:
475
476 Quadrangular wave patterns with sweep and envelope functions
477 Quadrangular wave patterns with envelope functions
478 Voluntary wave pattern
479 White noise
480
481 These four sounds can be controlled independantly and
482 then mixed separately for each of the output terminals.
483
484
485 Timer
486 -----
487
488 Sometimes it's useful to have a timer that interrupts at
489 regular intervals for routines that require periodic or
490 percise updates. The timer in the GameBoy has a selectable
491 frequency of 4096, 16384, 65536, or 262144 Hertz. This
492 frequency increments the Timer Counter (TIMA). When it
493 overflows, it generates an interrupt. It is then loaded
494 with the contents of Timer Modulo (TMA). The following
495 are examples:
496
497 ;This interval timer interrupts 4096 times per second
498
499 ld a,$ff
500 ldh (6),a ;Set TMA to divide clock by 1
501 ld a,4
502 ldh (7),a ;Set clock to 4096 Hertz
503
504 ;This interval timer interrupts 65536 times per second
505
506 ld a,256-4
507 ldh (6),a ;Set TMA to divide clock by 4
508 ld a,5
509 ldh (7),a ;Set clock to 262144 Hertz
510
511
512 Serial I/O
513 ----------
514
515 The serial I/O port on the Gameboy is a very simple setup
516 and is crude compared to standard RS-232 (IBM-PC) or RS-485
517 (Macintosh) serial ports. There are no start or stop bits
518 so the programmer must be more creative when using this port.
519
520 During a transfer, a byte is shifted in at the same time
521 that a byte is shifted out. The rate of the shift is deter-
522 mined by whether the clock source is internal or external.
523 If internal, the bits are shifted out at a rate of 8192Hz
524 (122 microseconds) per bit. The most significant bit is
525 shifted in and out first.
526
527 When the internal clock is selected, it drives the clock
528 pin on the game link port and it stays high when not used.
529 During a transfer it will go low eight times to clock
530 in/out each bit.
531
532 A programmer initates a serial transfer by setting bit 7 of
533 $FF02. An interrupt will then occur eight bit clocks later
534 if the serial interrupt is enabled.
535 If internal clock is selected and serial interrupt is
536 enabled, this interrupt occurs 122*8 microseconds later.
537 If external clock is selected and serial interrupt is
538 enabled, an interrupt will occur eight bit clocks later.
539
540 Initiating a serial transfer with external clock will
541 wait forever if no external clock is present. This allows
542 a certain amount of synchronization with each serial port.
543
544 The state of the last bit shifted out determines the
545 state of the output line until another transfer takes
546 place.
547
548 If a serial transfer with internal clock is performed
549 and no external GameBoy is present, all ones will be
550 shifted in on the receive byte.
551
552 The following code causes $75 to be shifted out the
553 serial port and a byte to be shifted into $FF01:
554
555 ld a,$75
556 ld ($ff01),a
557 ld a,$81
558 ld ($ff02),a
559
560
561 Interrupt Procedure
562 -------------------
563
564 The IME (interrupt master enable) flag is reset by DI and
565 prohibits all interrupts. It is set by EI and acknowledges
566 the interrupt setting by the IE register.
567
568 1. When an interrupt is generated, the IF flag will be set.
569 2. If the IME flag is set & the corresponding IE flag is
570 set, the following 3 steps are performed.
571 3. Reset the IME flag and prevent all interrupts.
572 4. The PC (program counter) is pushed onto the stack.
573 5. Jump to the starting address of the interrupt.
574
575 Resetting of the IF register, which was the cause of the
576 interrupt, is done by hardware.
577
578 During the interrupt, pushing of registers to be used
579 should be performed by the interrupt routine.
580
581 Once the interrupt service is in progress, all the
582 interrupts will be prohibited. However, if the IME flag
583 and the IE flag are controlled, a number of interrupt
584 services can be made possible by nesting.
585
586 Return from an interrupt routine can be performed be
587 either RETI or RET instruction.
588
589 The RETI instruction restores the IME state before an
590 interrupt. Any DI or EI done before the RETI is cancelled.
591
592 If a RET is used as the final instruction in an interrupt
593 routine, interrupts will remain disabled unless a EI was
594 used in the interrupt routine.
595
596 The interrupt will be acknowledged during opcode fetch
597 period of each instruction.
598
599
600 I/O Registers
601 -------------
602
603 FF00
604 Name - P1
605 Contents - Register for reading joy pad info
606 and determining system type. (R/W)
607
608 Bit 7 - Not used
609 Bit 6 - Not used
610 Bit 5 - P15 out port
611 Bit 4 - P14 out port
612 Bit 3 - P13 in port
613 Bit 2 - P12 in port
614 Bit 1 - P11 in port
615 Bit 0 - P10 in port
616
617 To determine what type of GameBoy this is write an 03
618 to this register then read it back. An Fx indicates
619 GameBoy or GameBoy Pocket, 3x indicates Super GameBoy.
620 (The 'x' indicates a don't care value.)
621
622 This is the matrix layout for register $FF00:
623
624
625 P14 P15
626 | |
627 P10-------O-Right----O-A
628 | |
629 P11-------O-Left-----O-B
630 | |
631 P12-------O-Up-------O-Select
632 | |
633 P13-------O-Down-----O-Start
634 | |
635
636
637 This is the logic in reading joy pad data:
638
639 Turn on P15 (bit 5) in $ff00
640 Wait a few clock cycles
641 read $ff00 into A
642 invert A - same as EOR #$FF - just reverse all
643 bits apparently the joy pad info
644 returned is like the C64 info.
645 0 means on, 1 means off. But logic
646 tells us that it should be the
647 other way around. So to make it
648 less confusing we just flip the bits!
649
650 AND A w/ #$0F - Get only the first four bits.
651 By turning on P15 we are trying
652 to read column P15 in the matrix
653 layout. It contains A,B,SEL,STRT
654
655 SWAP A - #$3f becomes #$f3, it swaps hi<->lo nibbles
656
657 store A in B for backup
658
659
660 Turn on P14 (bit 4) in $ff00
661 Wait a few more clock cycles
662 read $ff00 into A
663 invert A - just as above
664 AND A with #$0F - get first 4 bits
665 - By turning on P14 we get the
666 data for column P14 in the
667 matrix layout. It contains
668 U,D,L,& R.
669
670 OR A with B - put the two values together.
671
672 turn on P14 and P15 in $ff00 to reset.
673
674 The button values using the above method are such:
675 $80 - Start $8 - Down
676 $40 - Select $4 - Up
677 $20 - B $2 - Left
678 $10 - A $1 - Right
679
680 Let's say we held down A, Start, and Up.
681 The value returned in accumulator A would be $94
682
683 Example:
684 Game: Ms. Pacman
685 Address: $3b1
686
687 LD A,$20 <- bit 5 = $20
688 LD ($FF00),A <- turn on P15
689 LD A,($FF00)
690 LD A,($FF00) <- wait a few cycles
691 CPL <- complement (invert) EOR #$ff
692 AND $0F <- get only first 4 bits
693 SWAP A <- swap it
694 LD B,A <- store A in B
695 LD A,$10 <- bit 4 = $10
696 LD ($FF00),A <- turn on P14
697 LD A,($FF00)
698 LD A,($FF00)
699 LD A,($FF00)
700 LD A,($FF00)
701 LD A,($FF00)
702 LD A,($FF00) <- Wait a few MORE cycles
703 CPL <- complement (invert)
704 AND $0F <- get first 4 bits
705 OR B <- put A and B together
706
707 LD B,A <- store A in D
708 LD A,($FF8B) <- read old joy data from ram
709 XOR B <- toggle w/current button bit
710 AND B <- get current button bit back
711 LD ($FF8C),A <- save in new Joydata storage
712 LD A,B <- put original value in A
713 LD ($FF8B),A <- store it as old joy data
714
715
716 LD A,$30 <- turn on P14 and P15
717 LD ($FF00),A <- RESET Joypad?!
718 RET <- Return from Subroutine
719
720
721 FF01
722 Name - SB
723 Contents - Serial transfer data (R/W)
724
725 8 Bits of data to be read/written
726
727 FF02
728 Name - SC
729 Contents - SIO control (R/W)
730
731 Bit 7 - Transfer start flag
732 0: Non transfer
733 1: Start transfer
734
735 Bit 0 - Shift Clock
736 0: External Clock
737 1: Internal Clock (8192Hz)
738
739 FF04
740 Name - DIV
741 Contents - Divider Register (R/W)
742
743 This register is incremented 16384 times
744 a second. Writing any value sets it to $00.
745 FF05
746 Name - TIMA
747 Contents - Timer counter (R/W)
748
749 The timer generates an interrupt when it overflows.
750
751 FF06
752 Name - TMA
753 Contents - Timer Modulo (R/W)
754
755 When the TIMA overflows, this data will be loaded.
756
757 FF07
758 Name - TAC
759 Contents - Timer Control
760
761 Bit 2 - Timer Stop
762 0: Stop Timer
763 1: Start Timer
764
765 Bits 1+0 - Input Clock Select
766 00: 4.096 khz
767 01: 262.144 khz
768 10: 65.536 khz
769 11: 16.384 khz
770
771 FF0F
772 Name - IF
773 Contents - Interrupt Flag (R/W)
774
775 Bit 4: Transition from High to Low of Pin number P10-P13
776 Bit 3: Serial I/O transfer end
777 Bit 2: Timer Overflow
778 Bit 1: LCDC (see STAT)
779 Bit 0: V-Blank
780
781 The priority and jump address for the above 5 interrupts are:
782
783 Interrupt Priority Start Address
784
785 V-Blank 1 $0040
786 LCDC Status 2 $0048 - Modes 0, 01, 10
787 LYC=LY coincide (selectable)
788 Timer Overflow 3 $0050
789 Serial Transfer 4 $0058 - when transfer is complete
790 Hi-Lo Of P10-P13 5 $0060
791
792 * When more than 1 interrupts occur at the same time
793 only the interrupt with the highest priority can be
794 acknowledged. When an interrupt is used a '0' should
795 be stored in the IF register before the IE register
796 is set.
797
798
799 FF10
800 Name - NR 10
801 Contents - Sound Mode 1 register, Sweep register (R/W)
802
803 Bit 6-4 - Sweep Time
804 Bit 3 - Sweep Increase/Decrease
805 0: Addition (frequency increases)
806 1: Subtraction (frequency decreases)
807 Bit 2-0 - Number of sweep shift (n: 0-7)
808
809 Sweep Time: 000: sweep off - no freq change
810 001: 7.8 ms (1/128Hz)
811 010: 15.6 ms (2/128Hz)
812 011: 23.4 ms (3/128Hz)
813 100: 31.3 ms (4/128Hz)
814 101: 39.1 ms (5/128Hz)
815 110: 46.9 ms (6/128Hz)
816 111: 54.7 ms (7/128Hz)
817
818 The change of frequency (NR13,NR14) at each shift
819 is calculated by the following formula where
820 X(0) is initial freq & X(t-1) is last freq:
821
822 X(t) = X(t-1) +/- X(t-1)/2^n
823
824 FF11
825 Name - NR 11
826 Contents - Sound Mode 1 register, Sound length/Wave pattern duty (R/W)
827
828 Only Bits 7-6 can be read.
829
830 Bit 7-6 - Wave Pattern Duty
831 Bit 5-0 - Sound length data (t1: 0-63)
832
833 Wave Duty: 00: 12.5%
834 01: 25%
835 10: 50%
836 11: 75%
837
838 Sound Length = (64-t1)*(1/256) seconds
839 FF12
840 Name - NR 12
841 Contents - Sound Mode 1 register, Envelope (R/W)
842
843 Bit 7-4 - Initial volume of envelope
844 Bit 3 - Envelope UP/DOWN
845 0: Attenuate
846 1: Amplify
847 Bit 2-0 - Number of envelope sweep (n: 0-7)
848 (If zero, stop envelope operation.)
849
850 Initial volume of envelope is from 0 to $F.
851 Zero being no sound.
852
853 Length of 1 step = n*(1/64) seconds
854
855
856 FF13
857 Name - NR 13
858 Contents - Sound Mode 1 register, Frequency lo (W)
859
860 Lower 8 bits of 11 bit frequency (x).
861 Next 3 bit are in NR 14 ($FF14)
862
863 FF14
864 Name - NR 14
865 Contents - Sound Mode 1 register, Frequency hi (R/W)
866
867 Only Bit 6 can be read.
868
869 Bit 7 - Initial (when set, sound restarts)
870 Bit 6 - Counter/consecutive selection
871 Bit 2-0 - Frequency's higher 3 bits (x)
872
873 Frequency = 4194304/(32*(2048-x)) Hz
874 = 131072/(2048-x) Hz
875
876 FF16
877 Name - NR 21
878 Contents - Sound Mode 2 register, Sound Length; Wave Pattern Duty (R/W)
879
880 Only bits 7-6 can be read.
881
882 Bit 7-6 - Wave pattern duty
883 Bit 5-0 - Sound length data (t1: 0-63)
884
885 Wave Duty: 00: 12.5%
886 01: 25%
887 10: 50%
888 11: 75%
889
890 Sound Length = (64-t1)*(1/256) seconds
891
892 FF17
893 Name - NR 22
894 Contents - Sound Mode 2 register, envelope (R/W)
895
896 Bit 7-4 - Initial volume of envelope
897 Bit 3 - Envelope UP/DOWN
898 0: Attenuate
899 1: Amplify
900 Bit 2-0 - Number of envelope sweep (n: 0-7)
901 (If zero, stop envelope operation.)
902
903 Initial volume of envelope is from 0 to $F.
904 Zero being no sound.
905
906 Length of 1 step = n*(1/64) seconds
907
908 FF18
909 Name - NR 23
910 Contents - Sound Mode 2 register, frequency lo data (W)
911
912 Frequency's lower 8 bits of 11 bit data (x).
913 Next 3 bits are in NR 14 ($FF19).
914
915 FF19
916 Name - NR 24
917 Contents - Sound Mode 2 register, frequency hi data (R/W)
918
919 Only bit 6 can be read.
920
921 Bit 7 - Initial
922 Bit 6 - Counter/consecutive selection
923 Bit 2-0 - Frequency's higher 3 bits (x)
924
925 Frequency = 4194304/(32*(2048-x)) Hz
926 = 131072/(2048-x) Hz
927
928 FF1A
929 Name - NR 30
930 Contents - Sound Mode 3 register, Sound on/off (R/W)
931
932 Only bit 7 can be read
933
934 Bit 7 - Sound OFF
935 0: Sound 3 output stop
936 1: Sound 3 output OK
937
938 FF1B
939 Name - NR 31
940 Contents - Sound Mode 3 register, sound length (R/W)
941
942 Bit 7-0 - Sound length (t1: 0 - 255)
943
944 Sound Length = (256-t1)*(1/2) seconds
945
946 FF1C
947 Name - NR 32
948 Contents - Sound Mode 3 register, Select output level
949
950 Only bits 6-5 can be read
951
952 Bit 6-5 - Select output level
953 00: Mute
954 01: Produce Wave Pattern RAM Data as it is
955 (4 bit length)
956 10: Produce Wave Pattern RAM data shifted once
957 to the RIGHT (1/2) (4 bit length)
958 11: Produce Wave Pattern RAM data shifted twice
959 to the RIGHT (1/4) (4 bit length)
960
961 * - Wave Pattern RAM is located from $FF30-$FF3f.
962
963 FF1D
964 Name - NR 33
965 Contents - Sound Mode 3 register, frequency's lower data (W)
966
967 Lower 8 bits of an 11 bit frequency (x).
968
969 FF1E
970 Name - NR 34
971 Contents - Sound Mode 3 register, frequency's higher data (R/W)
972
973 Only bit 6 can be read.
974
975 Bit 7 - Initial flag
976 Bit 6 - Counter/consecutive flag
977 Bit 2-0 - Frequency's higher 3 bits (x).
978
979 Frequency = 4194304/(64*(2048-x)) Hz
980 = 65536/(2048-x) Hz
981
982 FF20
983 Name - NR 41
984 Contents - Sound Mode 4 register, sound length (R/W)
985
986 Bit 5-0 - Sound length data (t1: 0-63)
987
988 Sound Length = (64-t1)*(1/256) seconds
989
990 FF21
991 Name - NR 42
992 Contents - Sound Mode 4 register, envelope (R/W)
993
994 Bit 7-4 - Initial volume of envelope
995 Bit 3 - Envelope UP/DOWN
996 0: Attenuate
997 1: Amplify
998 Bit 2-0 - Number of envelope sweep (n: 0-7)
999 (If zero, stop envelope operation.)
1000
1001 Initial volume of envelope is from 0 to $F.
1002 Zero being no sound.
1003
1004 Length of 1 step = n*(1/64) seconds
1005
1006 FF22
1007 Name - NR 43
1008 Contents - Sound Mode 4 register, polynomial counter (R/W)
1009
1010 Bit 7-4 - Selection of the shift clock frequency of the
1011 polynomial counter
1012 Bit 3 - Selection of the polynomial counter's step
1013 Bit 2-0 - Selection of the dividing ratio of frequencies
1014
1015 Selection of the dividing ratio of frequencies:
1016 000: f * 1/2^3 * 2
1017 001: f * 1/2^3 * 1
1018 010: f * 1/2^3 * 1/2
1019 011: f * 1/2^3 * 1/3
1020 100: f * 1/2^3 * 1/4
1021 101: f * 1/2^3 * 1/5
1022 110: f * 1/2^3 * 1/6
1023 111: f * 1/2^3 * 1/7 f = 4.194304 Mhz
1024
1025 Selection of the polynomial counter step:
1026 0: 15 steps
1027 1: 7 steps
1028
1029 Selection of the shift clock frequency of the polynomial
1030 counter:
1031
1032 0000: dividing ratio of frequencies * 1/2
1033 0001: dividing ratio of frequencies * 1/2^2
1034 0010: dividing ratio of frequencies * 1/2^3
1035 0011: dividing ratio of frequencies * 1/2^4
1036 : :
1037 : :
1038 : :
1039 0101: dividing ratio of frequencies * 1/2^14
1040 1110: prohibited code
1041 1111: prohibited code
1042
1043 FF23
1044 Name - NR 30
1045 Contents - Sound Mode 4 register, counter/consecutive; inital (R/W)
1046
1047 Only bit 6 can be read.
1048
1049 Bit 7 - Inital
1050 Bit 6 - Counter/consecutive selection
1051
1052 FF24
1053 Name - NR 50
1054 Contents - Channel control / ON-OFF / Volume (R/W)
1055
1056 Bit 7 - Vin->SO2 ON/OFF
1057 Bit 6-4 - SO2 output level (volume) (# 0-7)
1058 Bit 3 - Vin->SO1 ON/OFF
1059 Bit 2-0 - SO1 output level (volume) (# 0-7)
1060
1061 Vin->SO1 (Vin->SO2)
1062
1063 By synthesizing the sound from sound 1
1064 through 4, the voice input from Vin
1065 terminal is put out.
1066 0: no output
1067 1: output OK
1068
1069 FF25
1070 Name - NR 51
1071 Contents - Selection of Sound output terminal (R/W)
1072
1073 Bit 7 - Output sound 4 to SO2 terminal
1074 Bit 6 - Output sound 3 to SO2 terminal
1075 Bit 5 - Output sound 2 to SO2 terminal
1076 Bit 4 - Output sound 1 to SO2 terminal
1077 Bit 3 - Output sound 4 to SO1 terminal
1078 Bit 2 - Output sound 3 to SO1 terminal
1079 Bit 1 - Output sound 2 to SO1 terminal
1080 Bit 0 - Output sound 0 to SO1 terminal
1081
1082 FF26
1083 Name - NR 52
1084 Contents - Sound on/off (R/W)
1085
1086 Only Bit 7, 3-0 can be read.
1087
1088 Bit 7 - All sound on/off
1089 0: stop all sound circuits
1090 1: operate all sound circuits
1091 Bit 3 - Sound 4 ON flag
1092 Bit 2 - Sound 3 ON flag
1093 Bit 1 - Sound 2 ON flag
1094 Bit 0 - Sound 1 ON flag
1095
1096 FF30 - FF3F
1097 Name - Wave Pattern RAM
1098 Contents - Waveform storage for arbitrary sound data
1099
1100 This storage area holds 32 4-bit samples
1101 that are played back upper 4 bits first.
1102
1103 FF40
1104 Name - LCDC (value $91 at reset)
1105 Contents - LCD Control (R/W)
1106
1107 Bit 7 - LCD Control Operation *
1108 0: Stop completely (no picture on screen)
1109 1: operation
1110
1111 Bit 6 - Window Tile Map Display Select
1112 0: $9800-$9BFF
1113 1: $9C00-$9FFF
1114
1115 Bit 5 - Window Display
1116 0: off
1117 1: on
1118
1119 Bit 4 - BG & Window Tile Data Select
1120 0: $8800-$97FF
1121 1: $8000-$8FFF <- Same area as OBJ
1122
1123 Bit 3 - BG Tile Map Display Select
1124 0: $9800-$9BFF
1125 1: $9C00-$9FFF
1126
1127 Bit 2 - OBJ (Sprite) Size
1128 0: 8*8
1129 1: 8*16 (height*width)
1130
1131 Bit 1 - OBJ (Sprite) Display
1132 0: off
1133 1: on
1134
1135 Bit 0 - BG Display
1136 0: off
1137 1: on
1138
1139 * - Stopping LCD operation (bit 7 from 1 to 0)
1140 must be performed during V-blank to work
1141 properly. V-blank can be confirmed when the
1142 value of LY is greater than or equal to 144.
1143
1144 FF41
1145 Name - STAT
1146 Contents - LCDC Status (R/W)
1147
1148 Bits 6-3 - Interrupt Selection By LCDC Status
1149
1150 Bit 6 - LYC=LY Coincidence (Selectable)
1151 Bit 5 - Mode 10
1152 Bit 4 - Mode 01
1153 Bit 3 - Mode 00
1154 0: Non Selection
1155 1: Selection
1156
1157 Bit 2 - Coincidence Flag
1158 0: LYC not equal to LCDC LY
1159 1: LYC = LCDC LY
1160
1161 Bit 1-0 - Mode Flag
1162 00: Entire Display Ram can be accessed
1163 01: During V-Blank
1164 10: During Searching OAM-RAM
1165 11: During Transfering Data to LCD Driver
1166
1167 STAT shows the current status of the LCD controller.
1168 Mode 00: When the flag is 00 it is the H-Blank period
1169 and the CPU can access the display RAM
1170 ($8000-$9FFF).
1171
1172 Mode 01: When the flag is 01 it is the V-Blank period
1173 and the CPU can access the display RAM
1174 ($8000-$9FFF).
1175
1176 Mode 10: When the flag is 10 then the OAM is being
1177 used ($FE00-$FE9F). The CPU cannot access
1178 the OAM during this period
1179
1180 Mode 11: When the flag is 11 both the OAM and display
1181 RAM are being used. The CPU cannot access
1182 either during this period.
1183
1184
1185 The following are typical when the display is enabled:
1186
1187 Mode 00 ---___---___---___---___---___---___---________________
1188
1189 Mode 01 _______________________________________--------------__
1190
1191 Mode 02 ___-_____-_____-_____-_____-_____-___________________-_
1192
1193 Mode 03 ____--____--____--____--____--____--__________________-
1194
1195
1196 The Mode Flag goes through the values 00, 02,
1197 and 03 at a cycle of about 109uS. 00 is present
1198 about 49uS, 02 about 20uS, and 03 about 40uS. This
1199 is interrupted every 16.6ms by the VBlank (01).
1200 The mode flag stays set at 01 for 1.1 ms.
1201
1202 FF42
1203 Name - SCY
1204 Contents - Scroll Y (R/W)
1205
1206 8 Bit value $00-$FF to scroll BG Y screen
1207 position.
1208
1209 FF43
1210 Name - SCX
1211 Contents - Scroll X (R/W)
1212
1213 8 Bit value $00-$FF to scroll BG X screen
1214 position.
1215
1216 FF44
1217 Name - LY
1218 Contents - LCDC Y-Coordinate (R)
1219
1220 The LY indicates the vertical line to which
1221 the present data is transferred to the LCD
1222 Driver. The LY can take on any value between
1223 0 through 153. The values between 144 and 153
1224 indicate the V-Blank period. Writing will
1225 reset the counter.
1226
1227 FF45
1228 Name - LYC
1229 Contents - LY Compare (R/W)
1230
1231 The LYC compares itself with the LY. If the
1232 values are the same it causes the STAT to set
1233 the coincident flag.
1234
1235 FF46
1236 Name - DMA
1237 Contents - DMA Transfer and Start Address (W)
1238
1239 The DMA Transfer (40*28 bit) from internal ROM or RAM
1240 ($0000-$F19F) to the OAM (address $FE00-$FE9F) can be
1241 performed. It takes 160 microseconds for the transfer.
1242
1243 40*28 bit = #140 or #$8C. As you can see, it only
1244 transfers $8C bytes of data. OAM data is $A0 bytes
1245 long, from $0-$9F.
1246
1247 But if you examine the OAM data you see that 4 bits are
1248 not in use.
1249
1250 40*32 bit = #$A0, but since 4 bits for each OAM is not
1251 used it's 40*28 bit.
1252
1253 It transfers all the OAM data to OAM RAM.
1254
1255 The DMA transfer start address can be designated every
1256 $100 from address $0000-$F100. That means $0000, $0100,
1257 $0200, $0300....
1258
1259 As can be seen by looking at register $FF41 Sprite RAM
1260 ($FE00 - $FE9F) is not always available. A simple routine
1261 that many games use to write data to Sprite memory is shown
1262 below. Since it copies data to the sprite RAM at the appro-
1263 priate times it removes that responsibility from the main
1264 program.
1265 All of the memory space, except high ram ($FF80-$FFFE),
1266 is not accessible during DMA. Because of this, the routine
1267 below must be copied & executed in high ram. It is usually
1268 called from a V-blank Interrupt.
1269
1270 Example program:
1271
1272 org $40
1273 jp VBlank
1274
1275 org $ff80
1276 VBlank:
1277 push af <- Save A reg & flags
1278 ld a,BASE_ADRS <- transfer data from BASE_ADRS
1279 ld ($ff46),a <- put A into DMA registers
1280 ld a,28h <- loop length
1281 Wait: <- We need to wait 160 microseconds.
1282 dec a <- 4 cycles - decrease A by 1
1283 jr nz,Wait <- 12 cycles - branch if Not Zero to Wait
1284 pop af <- Restore A reg & flags
1285 reti <- Return from interrupt
1286
1287
1288 FF47
1289 Name - BGP
1290 Contents - BG Palette Data (W)
1291
1292 Bit 7-6 - Data for Dot Data 11
1293 Bit 5-4 - Data for Dot Data 10
1294 Bit 3-2 - Data for Dot Data 01
1295 Bit 1-0 - Data for Dot Data 00
1296
1297 This selects the shade of gray you what for
1298 your BG pixel. Since each pixel uses 2 bits,
1299 the corresponding shade will be selected
1300 from here. The Background Color (00) lies at
1301 Bits 1-0, just put a value from 0-3 to
1302 change the color.
1303
1304 FF48
1305 Name - OBP0
1306 Contents - Object Palette 0 Data (W)
1307
1308 This selects the colors for sprite palette 0.
1309 It works exactly as BGP ($FF47).
1310 See BGP for details.
1311
1312 FF49
1313 Name - OBP1
1314 Contents - Object Palette 1 Data (W)
1315
1316 This Selects the colors for sprite palette 1.
1317 It works exactly as BGP ($FF47).
1318 See BGP for details.
1319
1320 FF4A
1321 Name - WY
1322 Contents - Window Y Position (R/W)
1323
1324 0 <= WY <= 143
1325
1326 WY must be greater than or equal to 0 and
1327 must be less than or equal to 143.
1328
1329 FF4B
1330 Name - WX
1331 Contents - Window X Position (R/W)
1332
1333 7 <= WX <= 166
1334
1335 WX must be greater than or equal to 7 and
1336 must be less than or equal to 166.
1337
1338
1339 Lets say WY = 80 and WX = 80.
1340 The window would be positioned as so:
1341
1342 0 80 159
1343 __________________________________________
1344 0 | | |
1345 | | |
1346 | | |
1347 | | |
1348 | | |
1349 | | |
1350 | |80 |
1351 80 |-------------------+----------------------|
1352 | 80 | |
1353 | | |
1354 | | Window Display |
1355 | | Here |
1356 | | |
1357 | | |
1358 | | |
1359 143 |___________________|______________________|
1360
1361
1362 OBJ Characters (Sprites) can still enter the
1363 window. So can BG characters.
1364
1365 FFFF
1366 Name - IE
1367 Contents - Interrupt Enable (R/W)
1368
1369 Bit 4: Transition from High to Low of Pin
1370 number P10-P13.
1371 Bit 3: Serial I/O transfer end
1372 Bit 2: Timer Overflow
1373 Bit 1: LCDC (see STAT)
1374 Bit 0: V-Blank
1375
1376 0: disable
1377 1: enable
Deleteddoc/HARDWARE.TXT +0−492
@@ -1,492 +0,0 @@
1 As it appears, the CPU used in GameBoy is not exactly Z80. Some of Z80
2 instructions and registers are missing while others are added:
3
4 * The "shadow" set of registers [BC',DE',HL',AF'] and the index registers
5 [IX,IY] are missing and, consequently, there are no DD and FD opcode tables.
6
7 * I/O ports are gone and so are all IN/OUT opcodes.
8
9 * HALT is interrupted even when interrupts are disabled.
10
11 * Following Z80 opcodes are changed:
12 ------------------------------------------------------------------------------
13 Code Z80 operation GameBoy operation
14 ------------------------------------------------------------------------------
15 08 xx xx EX AF,AF' LD (word),SP Save SP at given address
16 10 xx DJNZ offset STOP Meaning unknown
17 22 LD (word),HL LD (HLI),A Save A at (HL) and increment HL
18 2A LD HL,(word) LD A,(HLI) Load A from (HL) and increment HL
19 32 LD (word),A LD (HLD),A Save A at (HL) and decrement HL
20 3A LD A,(word) LD A,(HLD) Load A from (HL) and decrement HL
21 D3 OUTA (byte) No operation
22 D9 EXX RETI Enable interrupts and return
23 DB INA (byte) No operation
24 DD Prefix DD No operation
25 E0 xx RET PO LD (byte),A Save A at (FF00+byte)
26 E2 JP PO,word LD (C),A Save A at (FF00+C)
27 E3 EX HL,(SP) No operation
28 E4 CALL PO,word No operation
29 E8 xx RET PE ADD SP,offset Add signed offset to SP
30 EA xx xx JP PE,word LD (word),A Save A at given address
31 EB EX DE,HL No operation
32 EC CALL PE,word No operation
33 F0 xx RET P LD A,(byte) Load A from (FF00+byte)
34 F2 JP P,word No operation
35 F4 CALL P,word No operation
36 F8 xx RET M LDHL SP,offset Load HL with SP + signed offset
37 FA xx xx JP M,word LD A,(word) Load A from given address
38 FC CALL M,word No operation
39 FD Prefix FD No operation
40 ------------------------------------------------------------------------------
41
42
43 GameBoy memory map:
44 --------------------------- FFFF | 32kB ROMs are non-switchable and occupy
45 I/O ports + internal RAM | 0000-7FFF are. Bigger ROMs use one of two
46 --------------------------- FF00 | different bank switches. The type of a
47 Internal RAM | bank switch can be determined from the
48 --------------------------- C000 | internal info area located at 0100-014F
49 8kB switchable RAM bank | in each cartridge.
50 --------------------------- A000 |
51 16kB VRAM | MBC1 (Memory Bank Controller 1):
52 --------------------------- 8000 | Writing a value into 2000-3FFF area will
53 16kB switchable ROM bank | select an appropriate ROM bank at
54 --------------------------- 4000 | 4000-7FFF. Writing a value into 4000-5FFF
55 16kB ROM bank #0 | area will select an appropriate RAM bank
56 --------------------------- 0000 | at A000-C000.
57 |
58 | MBC2 (Memory Bank Controller 2):
59 | Writing a value into 2100-21FF area will
60 | select an appropriate ROM bank at
61 | 4000-7FFF. RAM switching is not provided.
62
63 Internal information area:
64
65 The internal information area is located at 0100-014F in each cartridge. It
66 contains following values:
67
68 0100-0103 A sequence of bytes 00 C3 xx xx where last two bytes contain the
69 starting address of a cartridge [lower byte first]. The first two
70 bytes of this sequence can be used as a "magic number" to
71 recognize GameBoy cartridges. When GameBoy starts, the control is
72 passed to address 0100 and then the sequence is interpreted as
73 NOP; JP <addr>.
74 0105-0133 Nintendo character area:
75 CE ED 66 66 CC 0D 00 0B 03 73 00 83 00 0C 00 0D
76 00 08 11 1F 88 89 00 0E DC CC 6E E6 DD DD D9 99
77 BB BB 67 63 6E 0E EC CC DD DC 99 9F BB B9 33 3E
78 0134-0143 Title of the game in ASCII terminated by zeroes
79 0144-0146 Not used
80 0147 Cartridge type:
81 0 - ROM ONLY 3 - ROM+MBC1+RAM+BATTERY
82 1 - ROM+MBC1 5 - ROM+MBC2
83 2 - ROM+MBC1+RAM 6 - ROM+MBC2+BATTERY
84 0148 ROM size:
85 0 - 256kBit = 32kB = 2 banks
86 1 - 512kBit = 64kB = 4 banks
87 2 - 1MBit = 128kB = 8 banks
88 3 - 2MBit = 256kB = 16 banks
89 4 - 4MBit = 512kB = 32 banks
90 0149 RAM size:
91 0 - None
92 1 - 16kBit = 2kB = 1 bank
93 2 - 64kBit = 8kB = 1 bank
94 3 - 256kBit = 32kB = 4 banks
95 0150-0151 Manufacturer code:
96 3301 - Nintendo
97 7901 - Accolade
98 A400 - Konami
99 014C Version number
100 014D Complement check
101 014E-014F Checksum [higher byte first] produced by adding all bytes of
102 a cartridge except for two checksum bytes together and taking
103 two lower bytes of the result.
104
105 Video controller:
106
107 Main GameBoy screen buffer [aka background] consists of 256x256 pixels or
108 32x32 tiles [8x8 pixels each]. Only 160x144 pixels can be displayed on the
109 screen. Registers SCROLLX and SCROLLY hold the coordinates of background to be
110 displayed in the left upper corner of the screen. Background wraps around the
111 screen i.e. when part of it goes off the screen, it appears on the opposite
112 side.
113 An area of VRAM known as Background Tile Table contains the numbers of tiles
114 to be displayed. It is organized as 32 rows of 32 bytes each. Each byte
115 contains a number of a tile to be displayed. Tile patterns are taken from the
116 Tile Pattern Table located either at 8000-8FFF or 8800-97FF. In the first
117 case, patterns are numbered with unsigned numbers from 0 to 255 [i.e. pattern
118 #0 lies at address 8000]. In the second case, patterns have signed numbers
119 from -128 to 127 [i.e. pattern #0 lies at address 9000]. The Tile Pattern
120 Table address for the background can be selected via LCDCONT register.
121 Besides background, there is also a "window" overlaying the background. The
122 window is not scrollable i.e. it is always displayed starting from its left
123 upper corner. The location of a window on the screen can be adjusted via
124 WNDPOSX and WNDPOSY registers. Screen coordinates of the top left corner of a
125 window are WNDPOSX-7,WNDPOSY. The tile numbers for the window are stored in
126 the Window Tile Table in the same way as background tiles are stored in the
127 Background Tile Table. The tile patterns are taken from the table at
128 8800-97FF and therefore have unsigned numbers.
129 Both background and window can be disabled or enabled separately via bits
130 in the LCDCONT register. There is also a special bit allowing to make window
131 "transparent". When window is transparent, pixels of color #0 are not being
132 displayed.
133
134 0 Background 255
135 0+--------------------------------------------+
136 | ^ |
137 | | |
138 | | SCROLLY |
139 | | |
140 | 0 v Physical Screen 159 |
141 | 0+------------------------+ |
142 | | ^ | |
143 | | | | |
144 | SCROLLX | | WNDPOSY | |
145 |<--------->| | | |
146 | | v | |
147 | | +----------+ |
148 | | WNDPOSX-7 | | |
149 | |<----------->| Window | |
150 | | | | |
151 | 143+-------------+----------+ |
152 | |
153 | |
154 | |
155 255+--------------------------------------------+
156
157 The tile images are stored in the Tile Pattern Tables. Each 8x8 image
158 occupies 16 bytes, where each 2 bytes represent a line:
159
160 Tile: Image:
161
162 .33333.. .33333.. -> 01111100 -> 7Ch
163 22...22. 01111100 -> 7Ch
164 11...11. 22...22. -> 00000000 -> 00h
165 2222222. <-- digits represent 11000110 -> C6h
166 33...33. color numbers 11...11. -> 11000110 -> C6h
167 22...22. 00000000 -> 00h
168 11...11. 2222222. -> 00000000 -> 00h
169 ........ 11111110 -> FEh
170 33...33. -> 11000110 -> C6h
171 11000110 -> C6h
172 22...22. -> 00000000 -> 00h
173 11000110 -> C6h
174 11...11. -> 11000110 -> C6h
175 00000000 -> 00h
176 ........ -> 00000000 -> 00h
177 00000000 -> 00h
178
179 As it was said before, there are two Tile Pattern Tables at 8000-8FFF and at
180 8800-97FF. The first one can be used for sprites and the background. Its tiles
181 are numbered from 0 to 255. The second table can be used for the background
182 and the window display and its tiles are numbered from -128 to 127.
183 GameBoy video controller can also display up to 40 sprites either in 8x8 or
184 in 8x16 mode. Sprite patterns have the same format as tiles, but they are
185 taken from the Sprite Pattern Table located at 8000-8FFF and therefore have
186 unsigned numbers. Sprite attributes reside in the Sprite Attribute Table [aka
187 OAM] at FE00-FE9F. OAM is divided into 40 4-byte blocks each of which
188 corresponds to a sprite. Blocks have the following format:
189
190 Byte0 Y position on the screen
191 Byte1 X position on the screen
192 Byte2 Pattern number 0-255 [notice that unlike tile numbers, sprite
193 pattern numbers are unsigned]
194 Byte3 Flags:
195 Bit7 Priority
196 Sprite is displayed in front of the window if this bit
197 is set to 1. Otherwise, sprite is shown behind the
198 window but in front of the background.
199 Bit6 Y flip
200 Sprite pattern is flipped vertically if this bit is
201 set to 1.
202 Bit5 X flip
203 Sprite pattern is flipped horizontally if this bit is
204 set to 1.
205 Bit4 Palette number
206 Sprite colors are taken from OBJ1PAL if this bit is
207 set to 1 and from OBJ0PAL otherwise.
208
209 GameBoy Sound:
210
211 There are two sound channels connected to the output terminals SO1 and SO2.
212 There is also a input terminal Vin connected to the cartridge. It can be
213 routed to either of both output terminals. GameBoy circuitry allows produces
214 sound in four different ways:
215
216 1. Quadrangular wave patterns with sweep and envelope functions
217 2. Quadrangular wave patterns with envelope functions
218 3. Voluntary wave pattern
219 4. White noise
220
221 These four sounds can be controlled independantly and then mixed separately
222 for each of the output terminals.
223
224 GameBoy I/O ports:
225
226 I/O ports are mapped to memory locations in FF00-FFFF area:
227 ------------------------------------------------------------------------------
228 FF00 -- JOYPAD [RW] Joypad port
229 Bit5 Bit4 | In order to scan the keys, output 0 into either Bit4
230 Bit3 DOWN START | or Bit5 of JOYPAD, wait for some time and read JOYPAD.
231 Bit2 UP SELECT | Bits 0-3 will be set to zeroes if corresponding
232 Bit1 LEFT B | buttons are pressed. Bits 6 and 7 are not used. Bits
233 Bit0 RIGHT A | 0-3 are connected to input lines P10-P13. Bits 4 and 5
234 | are connected to ouput lines P14 and P15.
235
236 Example:
237 ; Routine finding which buttons were pressed since the last check
238 LD A,20h ; Set 0 at the output line P14
239 LD (FF00h),A ;
240 LD A,(FF00h) ; Read JOYPAD several times to accomodate the noise
241 LD A,(FF00h) ;
242 CPL ; Bits 0-3 are now 1s if corresponding buttons pressed
243 AND 0Fh ; Extract lower 4 bits carrying button status...
244 SWAP A ; ...and move them into upper for bits
245 LD B,A ; At this point: B = START.SELECT.B.A.x.x.x.x
246 LD A,10h ; Set 0 at the output line P15
247 LD (FF00h),A ;
248 LD A,(FF00h) ; Read JOYPAD several times to accomodate the noise
249 LD A,(FF00h) ;
250 LD A,(FF00h) ;
251 LD A,(FF00h) ;
252 LD A,(FF00h) ;
253 LD A,(FF00h) ;
254 CPL ; Bits 0-3 are now 1s if corresponding buttons pressed
255 AND 0Fh ; Extract lower 4 bits carrying buttons' status...
256 OR B ; ...and combine them with 4 other button status bits
257 LD D,A ; At this point: D = START.SELECT.B.A.DOWN.UP.LEFT.RIGHT
258 LD A,(FF8Bh) ; Read old button status from RAM
259 XOR D ; Set 1s for buttons whose status has changed
260 AND D ; Extract buttons which were *pressed* since last check
261 LD (FF8Ch),A ; Save information of those buttons
262 LD A,D ; Update button status in RAM
263 LD (FF8Bh),A ;
264 LD A,30h ; Set 1s at both P14 and P15 lines
265 LD (FF00h),A ; [probably to reset the circuitry]
266
267 ------------------------------------------------------------------------------
268 FF01 -- SIODATA [RW] Serial I/O Data
269 ----------------------------------------------+---------------+---------------
270 FF02 -- SIOCONT [RW] Serial I/O Control | when set to 1 | when set to 0
271 Bit7 Transfer start flag | START | NO TRANSFER
272 Bit0 Serial I/O clock select | INTERNAL | EXTERNAL
273 ----------------------------------------------+---------------+---------------
274 FF04 -- DIVIDER [RW] Divider [meaning unknown]
275 ------------------------------------------------------------------------------
276 FF05 -- TIMECNT [RW] Timer Counter
277 This register contains constantly increasing number. The timer
278 interrupt occurs when this register overflows.
279 ------------------------------------------------------------------------------
280 FF06 -- TIMEMOD [RW] Timer Modulo
281 The contents of TIMEMOD are loaded into TIMECNT every time TIMECNT
282 overflows.
283 ----------------------------------------------+---------------+---------------
284 FF07 -- TIMCONT [RW] Timer Control | when set to 1 | when set to 0
285 Bit2 Start/Stop timer | COUNTING | STOPPED
286 Bit1-0 Timer clock select:
287 00 - 4096Hz 01 - 262144Hz 10 - 65536Hz 11 - 16384Hz
288 ----------------------------------------------+---------------+---------------
289 FF0F -- IFLAGS [RW] Interrupt Flags | when set to 1 | when set to 0
290 Bit4 Transition High->Low on pins P10-P13 | OCCURED | NO
291 Bit3 End of serial I/O transfer | OCCURED | NO
292 Bit2 Timer overflow | OCCURED | NO
293 Bit1 LCD controller interrupt [see LCDSTAT] | OCCURED | NO
294 Bit0 LCD vertical blanking impulse | OCCURED | NO
295 ----------------------------------------------+---------------+---------------
296 FF10 -- SNDREG10 [RW] Sweep [Sound Mode #1]
297 Bit6-4 Sweep time:
298 000: SWEEP OFF 010: 15.6ms 100: 31.3ms 110: 46.9ms
299 001: 7.8ms 011: 23.4ms 101: 39.1ms 111: 54.7ms
300 Bit3 Frequency increase[0]/decrease[1]
301 Bit2-0 Number of shifts
302 ------------------------------------------------------------------------------
303 FF11 -- SNDREG11 [RW] Sound Length/Pattern Duty [Sound Mode #1]
304 Bit7-6 Wave Pattern Duty [only these bits can be read]:
305 00: 12.5% 01: 25% 10: 50% 11: 75%
306 Bit5-0 Length of sound data
307 ------------------------------------------------------------------------------
308 FF12 -- SNDREG12 [RW] Control [Sound Mode #1]
309 Bit7-4 Initial value of envelope
310 Bit3 Envelope up[1]/down[0]
311 Bit2-0 Number of envelope sweep
312 ------------------------------------------------------------------------------
313 FF13 -- SNDREG13 [W] Frequency Low [Sound Mode #1]
314 Lower 8 bits of the 11bit frequency. Higher 3 bits are in SNDREG14.
315 ------------------------------------------------------------------------------
316 FF14 -- SNDREG14 [RW] Frequency High [Sound Mode #1]
317 Bit7 When 1 is written into this bit, sound restarts
318 Bit6 Counter/Consecutive selection [only this bit can be read]
319 Bit2-0 Higher 3 bits of the 11bit frequency
320 ------------------------------------------------------------------------------
321 FF16 -- SNDREG21 [RW] Sound Length/Pattern Duty [Sound Mode #2]
322 Bit7-6 Wave Pattern Duty [only these bits can be read]:
323 00: 12.5% 01: 25% 10: 50% 11: 75%
324 Bit5-0 Length of sound data
325 ------------------------------------------------------------------------------
326 FF17 -- SNDREG22 [RW] Control [Sound Mode #2]
327 Bit7-4 Initial value of envelope
328 Bit3 Envelope up[1]/down[0]
329 Bit2-0 Number of envelope step
330 ------------------------------------------------------------------------------
331 FF18 -- SNDREG23 [W] Frequency Low [Sound Mode #2]
332 Lower 8 bits of the 11bit frequency. Higher 3 bits are in SNDREG24.
333 ------------------------------------------------------------------------------
334 FF19 -- SNDREG24 [RW] Frequency High [Sound Mode #2]
335 Bit7 When 1 is written into this bit, sound restarts
336 Bit6 Counter/Consecutive selection [only this bit can be read]
337 Bit2-0 Higher 3 bits of the 11bit frequency
338 ------------------------------------------------------------------------------
339 FF1A -- SNDREG30 [RW] Control [Sound Mode #3]
340 Bit7 Sound on[1]/off[0]
341 ------------------------------------------------------------------------------
342 FF1B -- SNDREG31 [RW] Sound Length [Sound Mode #3]
343 ------------------------------------------------------------------------------
344 FF1C -- SNDREG32 [RW] Output Level [Sound Mode #3]
345 Bit6-5 Output Level:
346 00: MUTE 01: 100% 10: 50% 11: 25%
347 ------------------------------------------------------------------------------
348 FF1D -- SNDREG33 [W] Frequency Low [Sound Mode #3]
349 Lower 8 bits of the 11bit frequency. Higher 3 bits are in SNDREG34.
350 ------------------------------------------------------------------------------
351 FF1E -- SNDREG34 [RW] Frequency High [Sound Mode #3]
352 Bit7 When 1 is written into this bit, sound restarts
353 Bit6 Counter/Consecutive selection [only this bit can be read]
354 Bit2-0 Higher 3 bits of the 11bit frequency
355 ------------------------------------------------------------------------------
356 FF20 -- SNDREG41 [RW] Sound Length/Pattern Duty [Sound Mode #4]
357 Bit5-0 Length of sound data
358 ------------------------------------------------------------------------------
359 FF21 -- SNDREG42 [RW] Control [Sound Mode #4]
360 Bit7-4 Initial value of envelope
361 Bit3 Envelope up[1]/down[0]
362 Bit2-0 Number of envelope step
363 ------------------------------------------------------------------------------
364 FF22 -- SNDREG43 [RW] Polynomial Counter [Sound Mode #4]
365 Bit7-4 Shift clock frequency for the counter
366 0000: Dividing ratio of frequencies / 2
367 0001: Dividing ratio of frequencies / 2^2
368 0010: Dividing ratio of frequencies / 2^3
369 .... ....
370 1101: Dividing ratio of frequencies / 2^14
371 1100: Prohibited
372 1111: Prohibited
373 Bit3 Number of steps: 7 [1]/15 [0]
374 Bit2-0 Dividing ratio of frequences
375 000: f*2 010: f/2 100: f/4 110: f/6 where f = 4.194304Mhz/8
376 001: f*1 011: f/3 101: f/5 111: f/7
377 ------------------------------------------------------------------------------
378 FF23 -- SNDREG44 [RW] Frequency High [Sound Mode #4]
379 Bit7 When 1 is written into this bit, sound restarts
380 Bit6 Counter/Consecutive selection [only this bit can be read]
381 ------------------------------------------------------------------------------
382 FF24 -- SNDREG50 [RW] Channel and Volume Control
383 Bit7 Vin -> SO2 on[1]/off[0]
384 Bit6-4 Volume on SO2
385 Bit3 Vin -> SO1 on[1]/off[0]
386 Bit2-0 Volume on SO1
387 ------------------------------------------------------------------------------
388 FF25 -- SNDREG51 [RW] Sound Output Terminal Selector
389 Bit7 Sound 4 -> SO2 |
390 Bit6 Sound 3 -> SO2 |
391 Bit5 Sound 2 -> SO2 | SO1 and SO2 are two sound outputs connected to the
392 Bit4 Sound 1 -> SO2 | headphones. Vin is an input terminal in the cartridge
393 Bit3 Sound 4 -> SO1 | slot.
394 Bit2 Sound 3 -> SO1 |
395 Bit1 Sound 2 -> SO1 |
396 Bit0 Sound 1 -> SO1 |
397 ----------------------+-------------------------------------------------------
398 FF26 -- SNDREG52 [RW] Sound ON/OFF
399 Bit7 All sound on[1]/off[0]
400 Bit3 Sound 4 on[1]/off[0]
401 Bit2 Sound 3 on[1]/off[0]
402 Bit1 Sound 2 on[1]/off[0]
403 Bit0 Sound 1 on[1]/off[0]
404 ----------------------------------------------+---------------+---------------
405 FF40 -- LCDCONT [RW] LCD Control | when set to 1 | when set to 0
406 Bit7 LCD operation | ON | OFF
407 Bit6 Window Tile Table address | 9C00-9FFF | 9800-9BFF
408 Bit5 Window display | ON | OFF
409 Bit4 Tile Pattern Table address | 8000-8FFF | 8800-97FF
410 Bit3 Background Tile Table address | 9C00-9FFF | 9800-9BFF
411 Bit2 Sprite size | 8x16 | 8x8
412 Bit1 Color #0 transparency in the window | SOLID | TRANSPARENT
413 Bit0 Background display | ON | OFF
414 ----------------------------------------------+---------------+---------------
415 FF41 -- LCDSTAT [RW] LCD Status | when set to 1 | when set to 0
416 Bit6 Interrupt on scanline coincidence | ON | OFF
417 Bit5 Interrupt on controller mode 10 | ON | OFF
418 Bit4 Interrupt on controller mode 01 | ON | OFF
419 Bit3 Interrupt on controller mode 00 | ON | OFF
420 Bit2 Scanline coincidence flag | COINCIDENCE | NO COINCIDENCE
421 Bit1-0 LCD Controller mode:
422 00 - Horizontal blanking impulse [VRAM 8000-9FFF can be accessed by CPU]
423 01 - Vertical blanking impulse [VRAM 8000-9FFF can be accessed by CPU]
424 10 - OAM FE00-FE90 is accessed by LCD controller
425 11 - Both OAM FE00-FE90 and VRAM 8000-9FFF are accessed by LCD controller
426 ------------------------------------------------------------------------------
427 FF42 -- SCROLLY [RW] Background Vertical Scrolling
428 ------------------------------------------------------------------------------
429 FF43 -- SCROLLX [RW] Background Horizontal Scrolling
430 ------------------------------------------------------------------------------
431 FF44 -- CURLINE [RW] Current Scanline
432 This register contains the number of a screen line currently being
433 scanned. It can take values 0-153 where 144-153 indicate the vertical
434 blanking period. Writing into this register resets it.
435 ------------------------------------------------------------------------------
436 FF45 -- CMPLINE [RW] Scanline Comparison
437 When contents of CURLINE are equal to contents of CMPLINE, scanline
438 coincidence flag is set in the LCD status register and an interrupt
439 may occur.
440 ------------------------------------------------------------------------------
441 FF47 -- BGRDPAL [W] Background Palette
442 Bit7-6 Palette for color #3 |
443 Bit5-4 Palette for color #2 | 00 ------- 01 ------- 10 -------> 11
444 Bit3-2 Palette for color #1 | lightest darkest
445 Bit1-0 Palette for color #0 |
446 ------------------------------+-----------------------------------------------
447 FF48 -- OBJ0PAL [W] Sprite Palette #0
448 Bit7-6 Palette for color #3 |
449 Bit5-4 Palette for color #2 | 00 ------- 01 ------- 10 -------> 11
450 Bit3-2 Palette for color #1 | lightest darkest
451 Bit1-0 Palette for color #0 |
452 ------------------------------+-----------------------------------------------
453 FF49 -- OBJ1PAL [W] Sprite Palette #1
454 Bit7-6 Palette for color #3 |
455 Bit5-4 Palette for color #2 | 00 ------- 01 ------- 10 -------> 11
456 Bit3-2 Palette for color #1 | lightest darkest
457 Bit1-0 Palette for color #0 |
458 ------------------------------+-----------------------------------------------
459 FF4A -- WNDPOSY [RW] Window Y Position
460 WNDPOSY may assume values 0-143. It determines the vertical position
461 of the left upper corner of a window on the screen.
462 ------------------------------------------------------------------------------
463 FF4B -- WNDPOSX [RW] Window X Position
464 WNDPOSX may assume values 7-166. It determines the horizontal position
465 of the left upper corner of a window on the screen. The real position
466 is WNDPOSX-7.
467 ------------------------------------------------------------------------------
468 FF46 -- DMACONT [W] DMA Transfer Control
469 Writing to this register will cause a DMA transfer into OAM located
470 at FE00-FE9F. The written value determines the source address in a
471 following way: 00 -> 0000, 01 -> 0100, ... , 9A -> 9A00, ...
472 The DMA transfer takes about 160 nanoseconds.
473
474 Example:
475 ; Routine transferring 0400-049F into OAM
476 DI ; Disable interrupts
477 LD A,04h ; Transferring data from 0400h
478 LD (FF46h),A ; Start DMA transfer
479 LOOP: LD A,#40 ; Wait
480 DEC A ;
481 JR NZ,LOOP ;
482 EI ; Enable interrupts
483
484 ----------------------------------------------+---------------+---------------
485 FFFF -- ISWITCH [RW] Interrupt Enable/Disable | when set to 1 | when set to 0
486 Bit4 Transition High->Low on pins P10-P13 | ENABLED | DISABLED
487 Bit3 End of serial I/O transfer | ENABLED | DISABLED
488 Bit2 Timer overflow | ENABLED | DISABLED
489 Bit1 LCD controller interrupt [see LCDSTAT] | ENABLED | DISABLED
490 Bit0 LCD vertical blanking impulse | ENABLED | DISABLED
491 ----------------------------------------------+---------------+---------------
492
Deleteddoc/Todo +0−23
@@ -1,23 +0,0 @@
1 Todo list:
2
3 Priorities: 1 - must
4 2 - should
5 3 - nice to have
6
7 Features:
8
9 2 * Joystick support
10
11 1 * abilities to save the RAM (savegames)
12
13 1 * built-in debugger
14
15 3 * Add support for network games
16
17 Bugs:
18
19 1 * the speed is horribly slow, I don�t know how to raise it
20
21 1 * the sound is a bit strange :( It should be changed soon
22
23 3 * some few games like Tomb Raider are not working well
ModifiedhUGEDriver +1−1
@@ -1 +1 @@
1 Subproject commit 2a48e9c730b38130c9cf8d9d059aa48fcc317654 1 Subproject commit 35e51823205c323e2f3de3703fa38aa035cab81e